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A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V -5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors. © 1991-2012 IEEE.

Department of Electrical Engineering

World University root node

Department of Computer Science & Engineering

IEEE Transactions on Circuits and Systems for Video Technology

On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients

A high speed, low energy dynamic comparator using current recycling approach is proposed in this paper. The current flowing through the preamplifier during the regenerative phase is sensed and added to the regenerative nodes for high speed operation. The increment in power is further compensated using additional clock signal to prevent the full discharge of output nodes of the preamplifier. The comparator is designed and simulated in UMC 180 nm CMOS process at 1.8 V power supply. The performance of comparator is verified at different process corners. The designed comparator operates at a frequency of 500 MHz and consumes 162 fJ of energy. The variations in latency is observed from 10 ps to 1 ns for working range of 1 V. The Monte Carlo simulations are performed for 200 samples resulting in a mean offset of-0.0056 mV and standard deviation of 7.42 mV. © 2021 IEEE

Proceedings - IEEE International Symposium on Circuits and Systems

A high speed, low energy comparator based on current recycling approach

In this paper, a low-power readout using reconfigurable cyclic ADC for CMOS image sensors is proposed. It reduces the total number of pixels to be read by taking advantage of pixel correlation. The required number of ADC operations is reduced, resulting in power saving. In contrast to the existing pixel correlation-based approaches, which focus only on the intensity differences, in the proposed method, the polarity of the differences is also taken into account. It helps in preserving fine edges representing features such as texture. The discarded or unread pixels are interpolated on-chip while reconfiguring the ADC input range according to the interpolation step size. Furthermore, this reduces the number of ADC conversion cycles by 25% to 50% for interpolation steps of 16 LSB and 64 LSBs, respectively. The ADC is designed and fabricated in UMC 180-nm CMOS technology, and the proposed method is verified for standard test images. The reconstructed images incorporating ADC non-linearities result in average Pratt's FoM values of 0.88, 0.86, and 0.81 for 60%, 70%, and 74% compression, respectively. The corresponding best values achieved by the existing approaches are 0.86, 0.80, and 0.77, respectively. The improvement in FoM is observed due to the consideration of polarity information. The proposed technique results from 33% to 50% power saving for 80% compression in 512times512 image, using reconfigurable ADC. Therefore, it is suitable for a power efficient CMOS sensor design. © 2001-2012 IEEE.

IEEE Sensors Journal

A Power Efficient Image Sensor Readout with On-Chip δ -Interpolation Using Reconfigurable ADC

A 12-bit, programmable hybrid ADC for CMOS image sensor is proposed in this paper. The hybrid ADC internally uses cyclic-SAR architecture and results in an area efficient and high speed design. To minimize the total column ADC area, the elements of cyclic ADC are reused for SAR operation. The 12-bit programmable ADC can be operated either in high resolution mode or high speed mode depending on the number of bits allocated per stage. The prototype CMOS image sensor is designed and fabricated in AMS 350 nm CMOS OPTO process. A three-transistor pixel architecture followed by column parallel-readout circuit is implemented in a 9 µm column pitch. A prototype 128 × 96 image sensor consumes 62.7 mW of power at 3.3 V power supply. © 2020 IEEE

A CMOS image sensor with column-parallel cyclic-SAR ADC

Bio-signals such as electroencephalogram (EEG) contain low activity regions often called B-noise and high activity regions called active potentials. The high activity regions are more important as compared to their counterpart. In addition, the signals are considerably sparse in the low activity regions. Thus a full n-bit conversion of low activity samples into digital domain increases readout power and reduces data acquisition rate of analog to digital converter (ADC). To alleviate these problems, a reconfigurable cyclic ADC is presented in this paper. Input range and conversion cycles of the proposed ADC are varied according to the samples of the neural signal. The high activity region samples are resolved using conventional n-bits, however, the low activity region is resolved using less number of bits. This saves readout power and also reduces the digital data content. The proposed ADC is designed and fabricated in UMC 180 nm CMOS technology. The ADC operates at a sampling rate of 200 kS/s and consumes 61.8 μW of power. The chip occupies an area of 0.031 mm2. Using reconfiguration, the power saving of 28.6% is achieved compared to the conventional n-bit full conversion. © 2019 IEEE.

BioCAS 2019 - Biomedical Circuits and Systems Conference, Proceedings

A reconfigurable cyclic ADC for biomedical applications

A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/-0.5 LSB and +0.8/-0.9 LSB, respectively. The ADC consumes 435-μW of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 μm show that it is suitable for column-parallel readout in CMOS image sensors. © 1993-2012 IEEE.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A 12-bit, 2.5-bit/Phase column-parallel cyclic ADC

A superpixel based on-chip compression is proposed in this paper. Pixels are compared in spatial domain and the pixels with similar characteristics are grouped to form the superpixels. Only one pixel corresponding to each superpixel is read to achieve the compression. The on-chip compression circuit is designed and simulated in UMC 180 nm CMOS technology. For 70% compression, the proposed design results in about 33% power saving. The reconstruction of the compressed image is performed off-chip using bilinear interpolation. Further, two enhancement approaches are developed to improve the output image quality. The first approach is based on wavelet decomposition whereas the second approach uses a deep convolutional neural network. The proposed reconstruction technique takes two orders of magnitude lesser time as compared to the state-of-the-art technique. On an average, it results in peak signal to noise ratio (PSNR) and structural similarity index measure values of 30.999 and 0.9088 dB, respectively, for 70% compression in natural images. On the other hand, the best values observed from the existing approaches for the two metrics are 28.634 and 0.8115 dB, respectively. Further, the proposed technique is found useful for thermal image compression and reconstruction. The experiment shows that the compression of 86.2% can be achieved using the threshold of two intensity levels and the compressed image can be reconstructed with the PSNR of 45.87 dB. © 2018 IEEE.

Content Driven On-Chip Compression and Time Efficient Reconstruction for Image Sensor Applications

A low-power, high-speed on-chip compression and reconstruction technique is proposed in this paper. It takes the advantage of correlation between the consecutive pixels and reduces the total number of pixels to be read. The discarded pixels are interpolated on-chip using the proposed interpolation circuit. This reduces the total number of A/D conversions and hence results in power saving. The algorithm is verified for standard Lena image and about 5 dB better PSNR is observed for 20%- 90% compression, as compared to the existing techniques. Moreover, a promising performance is achieved on thermal image applications. The circuit is designed and simulated in AMS 350 nm OPTO process. For 57% compression, about 45% power saving in readout of the image sensor is observed. © 2018 IEEE.

Proceedings of IEEE Sensors

An On-Chip Interpolation Based Readout Scheme for Low-Power, High-Speed CMOS Image Sensors

A 12-bit, 1 MS/s, two-stage cyclic ADC, with novel 2.5-bit/cycle architecture is proposed in this paper. A 1.5-bit algorithm is used in a 2.5-bit framework, which reduces the required number of accurate comparators and power consumption by 42%. Further, the ADC shows 46% improvement in the conversion rate as compared to the state-of-the-art two-stage cyclic ADC. The proposed ADC is designed and fabricated in a standard 180 nm CMOS technology. The obtained values of DNL and INL are +0.5/-0.5 LSB and +0.8/-0.9 LSB respectively. The ADC consumes 0.8 mW of power and occupies an area of 0.045 mm2 with a FoM of 0.19 pJ/conversion-step. The proposed ADC when designed in a column pitch of 5.6 μm, will result in a frame-rate of 1000 frames/sec for a 1 Mpixel array. © 2018 IEEE.

A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors

A regeneration based BGR circuit is proposed in this paper. The regeneration using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature. This results in 60 % saving in power and over 80 % saving in area, when compared with the state-of-the-art trimming less BGR circuits. The obtained temperature coefficient is 33 ppm/° C for the temperature range 0° C-90° C. The circuit is designed and simulated in UMC 180nm CMOS process. The circuit consumes power of 40 nW and occupies an area of 0.003 mm2. The reference voltage of 819 mV is achieved at 1.2 V power supply. The power supply rejection ratio at 40 kHz is -47 dB. © 2017 IEEE.

Proceedings - International SoC Design Conference 2017, ISOCC 2017

A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs

A super-pixel based on-chip compression is proposed in this paper. The compression is achieved by reading only one sample for each super-pixel. The proposed technique and the corresponding circuit are simulated in MATLAB and UMC 180 nm CMOS technology, respectively. Higher values of PSNR are observed as compared to the state-of-the-art on-chip compression techniques. For the compression factor of 2, the implemented design results in 49% of power saving. © 2017 IEEE.

EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits

A super-pixel based on-chip image compression for high speed CMOS image sensors

A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 μW while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250-850 mV. © 2016 IEEE.

A low power low latency comparator for ramp ADC in CMOS imagers

We report for the first time, development of an efficient ethanol sensor using mild functionalized multiwalled carbon nanotubes (MWCNTs). A unique technique to functionalize MWCNT is reported to enhance the performance of the ethanol sensor based on it. The conventional functionalization techniques tend to damage physical structure of carbon nanotubes (CNTs) to a large extent and convert most of their sp2 bonds into sp3 bonded carbon atoms. This results in reduction of the available adsorption sites for ethanol vapors on the CNT surface and hence deteriorates the sensitivity. In this work, the functionalization of nanotubes is achieved through direct cycloaddition to π electrons of the CNT that does not hamper the physical structure of the nanotube. High resolution transmission electron microscopy (HRTEM) and Raman spectroscopy studies were employed to confirm the appropriate functionalization for better performance of the sensor. Electrical transport properties of the composites were also studied to understand the quality of the established CNT network. Out of the other functionalization technique, Diels Alder cyclo addition reaction based composite sensor was found to exhibit excellent performance and has an edge over the other reported CNT based sensor. © 2014 Elsevier Ltd. All rights reserved.

Materials Science in Semiconductor Processing

Enhancement in the performance of multi-walled carbon nanotube: Poly(methylmethacrylate) composite thin film ethanol sensors through appropriate nanotube functionalization

In wireless sensor networks, communication cost is higher as compared to computational cost, so it is important to minimize the amount of data transmission to extend the network lifetime. To minimize the volume of data to be transmitted, data aggregation is mostly used. As sensor nodes are being deployed in remote and unattented environments, they are prone to node compromise attacks and various other security issues. Hence, it is mandatory that data aggregation protocols must be designed by considering security issues on priority basis. Although, there is a trade-off between data aggregation and security of data, but both aspects are essential. Therefore it is challenging task to maintain data aggregation along with security in these networks. Recoverable Concealed Data aggregation Protocol for Homogeneous wireless sensor networks provides both security as well as aggregation. Despite of its strong security mechanism, this protocol is prone to Packet dropping attacks. This paper aims at detection of packet-dropping attack in Recoverable Concealed Data aggregation Protocol for Homogeneous wireless sensor networks. © 2015 IEEE.