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A low power low latency comparator for ramp ADC in CMOS imagers
, M. Sarkar
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 2016-July
Pages: 1466 - 1469
A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 μW while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250-850 mV. © 2016 IEEE.
About the journal
JournalData powered by TypesetProceedings - IEEE International Symposium on Circuits and Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.