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A CMOS image sensor with column-parallel cyclic-SAR ADC
, M.B. Karthik, M. Sarkar
Published in Institute of Electrical and Electronics Engineers Inc.
2020
Volume: 2020-October
   
Abstract
A 12-bit, programmable hybrid ADC for CMOS image sensor is proposed in this paper. The hybrid ADC internally uses cyclic-SAR architecture and results in an area efficient and high speed design. To minimize the total column ADC area, the elements of cyclic ADC are reused for SAR operation. The 12-bit programmable ADC can be operated either in high resolution mode or high speed mode depending on the number of bits allocated per stage. The prototype CMOS image sensor is designed and fabricated in AMS 350 nm CMOS OPTO process. A three-transistor pixel architecture followed by column parallel-readout circuit is implemented in a 9 µm column pitch. A prototype 128 × 96 image sensor consumes 62.7 mW of power at 3.3 V power supply. © 2020 IEEE
About the journal
JournalData powered by TypesetProceedings - IEEE International Symposium on Circuits and Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN02714310