Bio-signals such as electroencephalogram (EEG) contain low activity regions often called B-noise and high activity regions called active potentials. The high activity regions are more important as compared to their counterpart. In addition, the signals are considerably sparse in the low activity regions. Thus a full n-bit conversion of low activity samples into digital domain increases readout power and reduces data acquisition rate of analog to digital converter (ADC). To alleviate these problems, a reconfigurable cyclic ADC is presented in this paper. Input range and conversion cycles of the proposed ADC are varied according to the samples of the neural signal. The high activity region samples are resolved using conventional n-bits, however, the low activity region is resolved using less number of bits. This saves readout power and also reduces the digital data content. The proposed ADC is designed and fabricated in UMC 180 nm CMOS technology. The ADC operates at a sampling rate of 200 kS/s and consumes 61.8 μW of power. The chip occupies an area of 0.031 mm2. Using reconfiguration, the power saving of 28.6% is achieved compared to the conventional n-bit full conversion. © 2019 IEEE.