IIT J Academic Staff

&ldquo;IIT Jodhpur is committed to impart quality education to facilitate the creation of qualified, competent and responsible human resources to meet the emerging technological challenges of the world. It is working towards creating an equitable learning platform that is positive, accessible and effective in the face of the modern societal and scientific advancements.

Flexibility in curriculum, in all its academic programs, encompassing elements of teaching, research, creativity, innovation and entrepreneurship is the most unique feature of IIT Jodhpur. The Department of Science and Technology (DST), under the National Mission on Cyber Physical Systems, has identified IIT Jodhpur as a Technology &amp; Innovation Hub in the area of Augmented Reality and Virtual Reality. The institute has also been nominated as the coordinator for the Jodhpur City and Knowledge Cluster by the Office of Principal Scientific Adviser, Government of India.

The sprawling 852-acre IIT Jodhpur campus is a majestic tribute to the deep-rooted diverse cultural heritage of the region. The campus is an architectural masterpiece, which is slated to become an international exemplar of sustainability with net-zero energy, and advanced water and waste management strategies.&rdquo;

IIT Jodhpur

A MEMS capacitive sensor is emulated on a PCB for quick validation of CMOS interface circuit. In capacitive sensor, capacitance changes with external force; to mimic similar changes, controlled magnetic field is applied on emulated PCB capacitor. The dimension optimizations of interdigital capacitor are performed using CST software. The simulated values are milled on a FR4 sheet to make PCB capacitor. The simulated capacitance values are cross checked by making measurement using LCR meter on PCB capacitor and have a deviation of 6.5%. The complete MEMS emulator consists of PCB capacitor, permanent magnet controlled by screw gauge and gauss meter. A minimum change of 50 aF achieved over a base capacitance 1.9 pF. © 2020 IEEE.

World University root node

2020 IEEE 17th India Council International Conference, INDICON 2020

Emulation of MEMS Capacitive Sensor for CMOS Interface Circuit Validation

A current sensing analog-to-digital converter (CADC) targeting biomedical applications is proposed in this paper. The proposed architecture consists of a leaky integrate and fire (LIF) neuron model inspired from neuromorphic circuits along with digital control circuits and error correction circuit to enhance INL/DNL performance. The architecture is tuned for input signal ranging from 1 μA to 64 μA with power supply of 1/1.8 V for digital and analog blocks respectively. The design is implemented in 0.18 μm CMOS 1P4M triple-well process of Tower Jazz Semiconductor's technology. Total power consumption of the circuit is 1. 95 mW 48.86 μW respectively and achieves FoM of 331.6 71.24 pJ/conversion-step for the cases with and without error correction for 6-bits operation. © 2020 IEEE.

Neuromorphic Approach based Current Sensing Analog to Digital Converter for Biomedical Applications

The presented work describes an interconnected multi-server IoT network for monitoring and control of smart solar tree. The IoT enabled solar tree is introduced as a smart street light with air quality monitoring capability and has been implemented in the Central Electronics Engineering Research Institute, Pilani. The presented network is a three-layer architecture with a sensor node at the lowermost layer for collecting the sensor data. The solar tree server above it performs the sampling of the data by triggering the software for sensor node. Upon successful data collection, the tree server communicates the same to the central server which is responsible for aggregation, visualization, storage, analysis and control of all the connected solar trees. The paper also discusses the implementation aspect of the network and presents the collected data from the solar tree. The presented IoT network aims for enhancing the capabilities of the solar tree beyond just a power generation device to an application such as security, surveillance, pollution monitoring and many more. At present, the work discussed is towards self-sustained street light with ambient monitoring capability. © 2019 IEEE.

2019 10th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2019

IoT Platform to augment Solar Tree as Smart Highway Street Light with Ambient Monitoring Capability

This paper presents low power and highly tuneable LIF (modified) neuron model and its usage to implement reconfigurable digital logic gate. Simulations are done using Tower Jazz Semiconductor's 180nm technology and UMC 28 nm technology in Cadence virtuoso environment. Results show the advantage of neuromorphic approach in terms of re-configurability, power and area when compared to traditional logic gate designs. Reconfigurable gate performs AND/OR/NAND/NOR/XOR/XNOR. It works for both spiking input as well as DC input (current signal). Power consumption of reconfigurable gate designed using modified LIF is at least 45% less than the power consumption of CMOS gates. © 2019 IEEE.

Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019

Reconfigurable digital logic gate based on neuromorphic approach

Annals of Library and Information Studies

International conference on changing landscape of science &amp; technology libraries (Clstl 2019), 28 february – 02 march, 2019, iit gandhinagar

Silicon nanowire (SiNW) arrays are fabricated using complementary metal-oxide semiconductor (CMOS) compatible technology, for the detection of proteins, pH levels, cardiac biomarker troponin-T (cTnT) etc. The sensor output is fed to a 'current to frequency converter circuit'. Neuromorphic approach based low input referred noise frequency converter circuit is developed. The circuit generates a sequence of spikes with the help of Leaky integrate and fire neuron model (LIF) where firing delay maps to the strength of the stimulation across the array. The proposed read-out circuit is implemented using Tower Jazz Semiconductor's 0.18μm CMOS technology. The SiNW arrays are producing current change from 200pA to 1.6nA for a corresponding change of 50m V/0.5ng/ml protein concentration at the gate. The circuit is able to detect a change in current as low as 50pA and consuming IlμW power and 93×17μm 2 silicon area. © 2018 IEEE.

Department of Electrical Engineering

Proceedings of IEEE Sensors

Silicon Nanowire Based Platform Device for Chemical/Bio-Chemical Sensing Applications

This paper presents a tunable algorithmic analog to digital converter (ADC) for sensor interface application. The adoption of inverter based dynamic comparator and use of parallel switch (2 NMOS) in sample and hold circuit to reduce charge injection error are the key attributes of the proposed scheme. The circuit is designed using Tower Jazz Semiconductor's 0.18 μm CMOS technology, having total input capacitance of 500 fF. The estimated effective number of bits (ENOB) is 9 to 10 bit for a capacitive sensor with 585 μW power consumption. The capacitive sensor interface has FoM of 12.6 pJ/conversion for a base capacitance range of 40 to 50 pF and for piezoelectric sensor the base capacitance range is from 5 to 90 pF with an ENOB of 6 to 7 bit and power consumption 795.68 f.l W having FoM of 130 pJ/conversion. The conversion time of this proposed architecture is 46.06 μs. © 2018 IEEE.

Algorithmic ADC for Capacitive and Piezoelectric MEMS Sensor

A report on national conference on role of academic libraries for excellence in research (Roaler) 2018

Conventional charge pump circuit based on dynamic charge transfer switch (CTS) is limited by its efficiency due to the threshold voltage of MOS transistor. This paper proposes an improved dynamic CTS based charge pump circuit by modifying the conventional circuit architecture at the output stage by a PMOS transistor with appropriate control signals. A four-stage dynamic CTS based charge pump circuit with pumping capacitance of 50 pF, clock frequency of 20MHz and load current of 100µA is designed and simulated in Cadence environment using UMC 0.18µm CMOS technology. As compared to conventional architecture, this modification has reduced the voltage loss at the output to 1.3% as compared to 9% for 1V input and 6% as compared to 20% for 0.3V input voltage. The core dimension of the layout is 750µm×530µm. © Springer Nature Singapore Pte Ltd 2017.

Communications in Computer and Information Science

An improved highly efficient low input voltage charge pump circuit

Arsenic that adversely affects human health is frequently reported in certain regions in India and other parts of the world. A low cost, portable, and eco-friendly field test system is required to monitor the levels of arsenic in drinking water procured from different tube wells and open wells. This paper presents the construction of biosensor strain by transforming E. coliDH 5α with the plasmid pJSKV51 carrying in-frame promoter operator region as well as entire arsR gene, part of arsD gene and enhanced green fluorescent protein (EGFP) gene. This strain was able to induce EGFP in presence of arsenic III ion. This paper further presents a novel EGFP-based bio-electronic sensing methodology to develop a low-cost battery operated system to measure the fluorescence emitted by biosensor strain and display the numerical values of the concentrations of arsenic in water samples. In this method, a blue light of 480 nm excites the EGFP to produce a green fluorescence signal in proportion to arsenic concentration. The developed device includes a compact embedded system to measure the signal fluorescence using light sensor, programmable controllers and liquid crystal display to show the corresponding concentration of the arsenic in ppb. The experimental results show that the system can detect and display over a range from 5 to 100 ppb. © 2001-2012 IEEE.