This paper presents a tunable algorithmic analog to digital converter (ADC) for sensor interface application. The adoption of inverter based dynamic comparator and use of parallel switch (2 NMOS) in sample and hold circuit to reduce charge injection error are the key attributes of the proposed scheme. The circuit is designed using Tower Jazz Semiconductor's 0.18 μm CMOS technology, having total input capacitance of 500 fF. The estimated effective number of bits (ENOB) is 9 to 10 bit for a capacitive sensor with 585 μW power consumption. The capacitive sensor interface has FoM of 12.6 pJ/conversion for a base capacitance range of 40 to 50 pF and for piezoelectric sensor the base capacitance range is from 5 to 90 pF with an ENOB of 6 to 7 bit and power consumption 795.68 f.l W having FoM of 130 pJ/conversion. The conversion time of this proposed architecture is 46.06 μs. © 2018 IEEE.