Department of Electrical Engineering

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IIT Jodhpur

We present CMOS compatible fabrication technique for silicon nanowire (SiNW) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medical sensors; all in a CMOS friendly manner. The physical and electrical characterization of the SiNW is also presented in this paper. © World Scientific Publishing Company.

World University root node

International Journal of Nanoscience

Silicon nanowires formation in CMOS compatible manner

This paper describes a control scheme for a MIMO system using backstepping method. Backstepping method is preferred in case of uncertainties in the process and constraints acting on the control input. In the present work, backstepping method for a PMTD process is investigated in order to maintain the concentration and volume of the dye bath thereby reduce the tailing effect. The proposed control strategy is designed and simulated using Matlab/ simulink and results are presented to validate the proposed control scheme. © 2006 IEEE.

2006 1st IEEE Conference on Industrial Electronics and Applications

Backstepping technique based nonlinear controller for a textile dyeing process

This paper proposes a composite output feedback controller which consists of periodic output feedback and fast output sampling feedback controller. Each of the controllers is designed to suppress the particular vibration mode. The proposed controller is applied to control the first two vibration modes of a piezoelectric actuated cantilever beam. The performance of the controller is shown by simulation and experimental results. A digital control system that consists of simulink modeling software and dSPACE 1104 controller board is used for identification and control.

Proceedings of the IEEE International Conference on Industrial Technology

Design and experimental evaluation of composite output feedback control for smart structures

The behavior of the system in sliding mode is determined by the sliding manifold upon which the system states are constrained. Sliding hyperplanes, being the most generally used manifolds guarantee asymptotic stability of the system in the sliding mode. This would mean that the system states converge to the origin, but generally at an infinite time. Terminal sliding mode (TSM) control [55] aims at designing a sliding mode control strategy that would guarantee a finite time convergence to the origin. This is accomplished by using a nonlinear sliding line which results in finite time convergence [30]. The concept of terminal sliding mode in continuous time systems has been studied in detail [56, 79–81]. The discrete-time equivalent of the continuous time terminal sliding mode control would be investigated in this chapter. © Springer-Verlag Berlin Heidelberg 2006.

Lecture Notes in Control and Information Sciences

6 Discrete-time terminal sliding mod: Concept

Systems with uncertainties and disturbances are common in practice. In some cases, these disturbances are unmatched. Moreover, in most cases the entire state information is also not available for control purpose. This note proposes a control algorithm for achieving quasi-sliding mode in discrete-time linear time-invariant (LTI) systems with bounded unmatched uncertainties. A multirate output feedback based strategy is used for this purpose. The proposed algorithm is illustrated through an example. © 2006 IEEE.

IEEE Transactions on Automatic Control

Discrete sliding mode control of systems with unmatched uncertainty using multirate output feedback

Discrete-time sliding mode control using multirate output feedback

Silicon nanowires (SiNW) were fabricated on bulk Silicon and SOI wafers by means of conventional Si process technology. The nanowires were formed by stress-limited oxidation of Si beams pre-patterned on the wafer. Single or double vertically self-aligned wires were obtained depending on the bulk or SOI wafer used and also on the depth of silicon beam etched. The resulting nanowires exhibit triangular cross-section that can be converted to circular shape by annealing at high temperatures, exploiting the visco-elastic properties of SiO2 and Si. Electrical measurements on single nanowire show that the resistance scales with length demonstrating consistent cross-sectional dimension in wires of different length. The nanowires formed on SOI wafers were also characterized as channels in FET configuration, using substrate as gate electrode. This technique can be exploited for realizing several nano-electronics, NEMS and biosensor applications in bulk silicon or SOI wafers, all in a CMOS compatible manner. © 2006 IEEE.

NanoSingapore 2006: IEEE Conference on Emerging Technologies - Nanoelectronics - Proceedings

Transport characteristics of Si nanowires in bulk silicon and SOI wafers

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (ε ∼ -1.07%) strained-Si0.55 Ge0.45 and the n-MOSFET in tensile-strained Si over the relaxed Si0.80 Ge0.20 exhibited significant hole (enhancement factor ∼ 1.9) and electron (enhancement factor ∼ 1.6) mobility enhancements over the Si reference. © 2006 IEEE.

IEEE Electron Device Letters

A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator

Fully CMOS compatible Silicon-nanowire (SiNW) Gate-All-Around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/μm for n-FET, 1.3 mA/μm for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-V8 oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well.

Technical Digest - International Electron Devices Meeting, IEDM

Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with ≤ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (∼ 63 mV/dec), low drain-induced barrier lowering (∼ 10 mV/V), and with ION/IOFF ratio of ∼ 106. High drive currents of ∼ 1.5 and ∼ 1.0 mA/μm were achieved for 180-nm-long n- and p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body. © 2006 IEEE.