This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with ≤ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (∼ 63 mV/dec), low drain-induced barrier lowering (∼ 10 mV/V), and with ION/IOFF ratio of ∼ 106. High drive currents of ∼ 1.5 and ∼ 1.0 mA/μm were achieved for 180-nm-long n- and p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body. © 2006 IEEE.