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Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
Singh N., Lim F.Y., Fang W.W., Rustagi S.C., Bera L.K., Tung C.H., Hoe K.M., Omampuliyur S.R., Tripathi D., Adeyeye A.O.Show More
Published in
2006
Abstract
Fully CMOS compatible Silicon-nanowire (SiNW) Gate-All-Around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/μm for n-FET, 1.3 mA/μm for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-V8 oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well.
About the journal
JournalTechnical Digest - International Electron Devices Meeting, IEDM
ISSN01631918
Open AccessNo