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Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performancePublished in
2006
Fully CMOS compatible Silicon-nanowire (SiNW) Gate-All-Around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/μm for n-FET, 1.3 mA/μm for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-V8 oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well.
Topics: Nanowire (54)%54% related to the paper, Threshold voltage (52)%52% related to the paper, MOSFET (51)%51% related to the paper and CMOS (51)%51% related to the paper
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About the journal
| Journal | Technical Digest - International Electron Devices Meeting, IEDM |
|---|---|
| ISSN | 01631918 |
| Open Access | No |
Authors (1)
Ajay Agrawal- Department of Electrical Engineering IIT Jodhpur
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