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A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator
L.K. Bera, M. Mukherjee-Roy, B. Abidha, , W.Y. Loh, C.H. Tung, R. Kumar, A.D. Trigg, Y.L. Foo, S. TripathyShow More
Published in
Volume: 27
Issue: 5
Pages: 350 - 353
This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (ε ∼ -1.07%) strained-Si0.55 Ge0.45 and the n-MOSFET in tensile-strained Si over the relaxed Si0.80 Ge0.20 exhibited significant hole (enhancement factor ∼ 1.9) and electron (enhancement factor ∼ 1.6) mobility enhancements over the Si reference. © 2006 IEEE.
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JournalIEEE Electron Device Letters