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A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise (SSN) is presented. The EBG structure with stopband from 750 MHz to 5.10 GHz is designed, fabricated and validated using network analyzer. Simulation results are verified by measurements and compared with the earlier published structures. Suppression of resonant cavity modes of power plane by EBG structure is also shown. The adoption of EBG structure in power deliver network is recommended to reduce the high frequency noise coupling between neighboring devices. These structures further help in better EMI/EMC compliance of the product by attenuating the propagation of high frequency noise between devices. The EBG structure usage can be on board, package or at die level. © 2013 IEEE.

Department of Electrical Engineering

World University root node

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013

A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits

Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board are found using particle swarm optimization. A novel and accurate methodology is presented which can be used for any high speed Power delivery Network. © 2013 IEEE.

Proceedings - International Symposium on Quality Electronic Design, ISQED

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization

Random jitter (RJ) estimation based on Tail Fit algorithm are generally inaccurate in presence of deterministic components like the presence of sinusoidal jitter (SJ) and duty cycle distortion (DCD). Addition of deterministic jitter changes the standard deviation of the tail region of resulting jitter probability density function. A new methodology for random jitter estimation in presence of sinusoidal jitter and duty cycle distortion is presented. The method involves calculation of mathematical correction factor, which are derived and used to calculate the precise value of random jitter. The proposed methodology is validated by inducing known jitter sources in real channel simulator of ADS from Agilent. © 2013 IEEE.

Mitigating the impact of sinusoidal jitter and duty cycle distortion on random jitter estimation by Tailfit algorithm

To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Optimum number of capacitors and their values, by which impedance of loaded board is matched below the target impedance of the system, are found. © 2012 IEEE.

Maintaining power integrity by damping the cavity-mode anti-resonances' peaks on a power plane by particle swarm optimization

This chapter is an overview of the applications of particle swarm optimization for circuits and systems. The chapter is targeted for the Analog/RF circuits and systems designers. Design automation, modeling, optimization and testing of analog/RF circuits using particle swarm optimization is presented. Various applications of particle swarm optimization for circuits and systems are explained by examples. © 2013, IGI Global.

Swarm Intelligence for Electric and Electronic Engineering

Design automation, modeling, optimization, and testing of analog/RF circuits and systems by particle swarm optimization

Swarm intelligence is applied to a module of high speed system design problem. To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented. The optimal values and the optimal positions of the decoupling capacitors are found using three different swarm intelligence methods -particle swarm optimization, cuckoo search method and firefly algorithm. Optimum values and locations of decoupling capacitors are obtained, by which anti-resonances' peaks of loaded board are minimized. © 2012 IEEE.

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms

System-level signal integrity (SI) and power integrity (PI) problems are taken into account. System-level simulation of high-speed systems with effect of external environment is described. SI and PI issues with complete analysis of package, board, termination, squid card, and decoupling network are shown. Common problems of simulations-passivity violation, stability, causality, and interoperability, are also discussed.

IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India)

Signal integrity and power integrity issues at system level

Phase Noise optimization for RF oscillator using Design of Experiments (DOE) is presented. The constraint of keeping frequency deviation minimum is taken in to account by ANOVA and nominal-the-best approach of Taguchi methods. Phase Noise of the oscillator is improved by -3.6 dB with frequency deviation of 0.04 %. Power consumption is also reduced by 3.2 mW. © 2011 IEEE.

Midwest Symposium on Circuits and Systems

Optimizing phase noise of 2 GHz RF oscillator with minimum frequency deviation

Optimizing Gain of an RF Amplifier using Design of Experiments (DOE), is presented. The constraints of keeping minimum deviations in both frequency and Noise Figure (NF) is taken in to account by ANOVA and nominal-the-best approach of Taguchi Methods. Gain of the amplifier is improved by 2.4 dB with frequency and NF deviations of 0% each. © 2011 IEEE.

2011 International Symposium on Integrated Circuits, ISIC 2011

Optimizing Gain of 5 GHz RF amplifier keeping minimum deviation in center frequency and noise figure

This paper presents stochastic convergence analysis of particle swarm optimization algorithm involving randomness and applying the results to the Analog RF Circuits to optimize the circuit parameters. In every iteration, each particle position is represented as vector and the standard particle swarm algorithm determined by positive real tipple {w,c 1,c 2}. Comparisons for convergence are presented with respect to fixed tipple {w,c 1,c 2} and random tipple {w,c 1,c 2}. Various results show that the randomness in defining new position to particle leads to better convergence property. Also, exploration and exploitation trade off are discussed with examples. It is demonstrated that each particle undergoes both exploration and exploitation in convergence process; if the randomness in the particle generation is considered. The parameters considered for RF circuit are cutoff frequency, Phase Noise and Signal to Noise Ratio (SNR). Results are compared between both fixed values and random values of parameters in convergence analysis of PSO. © 2011 IEEE.

Proceedings of the 2011 World Congress on Information and Communication Technologies, WICT 2011

Optimization of analog RF circuit parameters using randomness in particle swarm optimization

Signal Integrity (SI) and Power Integrity (PI) are the most inportant characteristics for system level design, simulation and analysis of high speed systems. In this paper, HSLINK system is optimized for better SI and PI. Linear models for eye amplitude and jitter are derived by Design of Experiments (DOE). Cost effective solution strategy is also presented using linear models obtained. © 2011 IEEE.

Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Cost-effective optimization of serial link system for Signal Integrity and Power Integrity

Designing of an Asymmetric RF Oscillator using Design of Experiments is presented and Taguchi Orthogonal Array is used for the same. Dependence of various physical parameters on output Quality Parameter, which is Phase Noise, is shown by curves. The improvement in Phase Noise is around 1.5 dB. All in all, Designing of an Asymmetric Oscillator is shown using Design of Experiments.

Proceedings of Papers - 5th European Conference on Circuits and Systems for Communications, ECCSC'10

Designing Asymmetric 2.2 GHz RF Oscillator by Design of Experiments using Taguchi methods

Signal Integrity (SI) and Power Integrity (PI) are the most critical issues for higher operational speeds in semiconductor industry. This work identifies and optimizes the parameters of board, package and termination environment, influencing the signal integrity and power integrity of serial link. System level model has been created for USB HSLINK taking into account the external parameters like board, package, measurement environment which influence the performance of the channel. Parameters variations appearing from manufacturability constraints, material property constraints, design tolerance etc affecting the serial link performance has been optimized using Taguchi method based on statistical co-analysis. Using the Taguchi statistical techniques, sensitivity analysis on parameter variations affecting HSLINK performance is analyzed and optimized for desired performance. ©2010 IEEE.

2010 IEEE International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2010

Robust optimization of serial link system for signal integrity and power integrity

Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level channel Bit Error Rate requirement for high bandwidth systems. The parameters which influence the channel and it's interconnect environment are primarily governed by signal integrity and power integrity requirements. In this paper, System Level Robustness Analysis of High Speed Serial Links is demonstrated with external environment considerations taken into account. A strong correlation between measured and simulated results is shown. A generic methodology for high speed serial links is presented with complete analysis of package, board, termination, Signal Quality inrush Droop/Drop (SQiDD), decoupling network etc. © 2009 IEEE.

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Signal integrity and power integrity methodology for robust analysis of on-the-board system for high speed serial links

Recent inventions in VLSI technology lead IT consumer market to be prepared for business of new products everyday. With these tech-advancements, a new motherboard is designed for every release of a new processor in the form of fixed ASIC thus makes the old motherboards useless. This leads to two big problems of E-waste as well as Technology upgradation cost. To overcome these problem, authors have already proposed Three-Tier architecture for the computer processors that introduces a Reconfigurable Master Processor in FPGA, controling all other old technology processors. This uses a smart OS named kshtizindial-OS (KIOS), at higher tier, Reconfigurable FPGA (Master Processor) at middle tier and the old processors at lower tier. This architecture emphasizes on an innovative concept of a very smart and auto-reconfigurable Operating System, KIOS with a reconfigurable CPU in FPGA that controls and reuses the old processors. The KIOS will incorporate the feature of soft-reconfiguration or auto-updation such that it can be able to reconfigure the FPGA as per the need of new release. All the tasks in the three tier architecture of KIOS is managed and interfaced for user by an application cum system software. Serially, these all tasks are presented here by a seven step process. This new architecture also contains new techniques of implementation for main memory, cache memory, bus architectures data and address mapping, multiprocessor scheduling and clock management. © 2007 IEEE.