IIT J Academic Staff

&ldquo;IIT Jodhpur is committed to impart quality education to facilitate the creation of qualified, competent and responsible human resources to meet the emerging technological challenges of the world. It is working towards creating an equitable learning platform that is positive, accessible and effective in the face of the modern societal and scientific advancements.

Flexibility in curriculum, in all its academic programs, encompassing elements of teaching, research, creativity, innovation and entrepreneurship is the most unique feature of IIT Jodhpur. The Department of Science and Technology (DST), under the National Mission on Cyber Physical Systems, has identified IIT Jodhpur as a Technology &amp; Innovation Hub in the area of Augmented Reality and Virtual Reality. The institute has also been nominated as the coordinator for the Jodhpur City and Knowledge Cluster by the Office of Principal Scientific Adviser, Government of India.

The sprawling 852-acre IIT Jodhpur campus is a majestic tribute to the deep-rooted diverse cultural heritage of the region. The campus is an architectural masterpiece, which is slated to become an international exemplar of sustainability with net-zero energy, and advanced water and waste management strategies.&rdquo;

IIT Jodhpur

This work presents the rigorous formulation of input referred offset voltage for differential amplifier, having the input pair devices in subthreshold region of operation. The formulation has been verified in 0.35 μm and 0.18 μm CMOS technologies by using Monte Carlo Simulation. Minimization of 1/f noise is the additional advantage of this method. © 2010 IEEE.

World University root node

Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

DC offset modeling and noise minimization for differential amplifier in subthreshold operation

Web 2 . 0 Applications in Reaching Out to Asian Distance Learners

Blogging is a relatively recent phenomenon, and its use in academic libraries is in nascent stage. The authors of this chapter use blogs as part of their outreach to patrons, though in slightly different contexts and for slightly different purposes. Blogging can be an important component of digital libraries, one that allows for timely two-way communication of news, information, bibliographic instruction, and the like. While challenges have been raised to the worth and value of academic library blogs (e.g., Gorman, 2005), the authors believe, based on the research and their experience, that blogging is a useful tool for academic librarians and digital libraries. © 2010, IGI Global.

Developing Sustainable Digital Libraries: Socio-Technical Perspectives

Building digital libraries: Role of social (open source) software

Changing roles in the changing information world: a study of change and its management for library and information professionals

This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 μm Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1mV, SNR of 60dB. The layout of the sample hold circuit occupies an area of 0.007mm2 and consumes 1.7 mW of power.

2009 International Conference on Emerging Trends in Electronic and Photonic Devices and Systems, ELECTRO '09

Design of pseudo flip-around sample hold- circuit for 10-bit, 5-Msamples/sec pipeline ADC

Recently, the industry has focused a great deal on the use of non-planar multi-gate device structures. Many drain current models are available for undoped thin silicon channel double-gate (DG) silicon-on-insulator (SOI) MOSFET, but these models do not take charge coupling effect into account leading to an error of more than 20 percent for silicon channel thicknesses below 30nm. Hence, we present here a modified drain current model based on the widely accepted and studied Ortiz-Conde suface potential model. The proposed model incorporates charge-coupling effect which comes into play in thin silicon channel multi-gate devices due to interaction of the multiple gates. The results of both the Ortiz-Conde's surface potential based model and the modified current model have been compared with simulated results obtained from Taurus-Davinci simulator. The modified model has an error percentage less than 4% even for channel widths as low as 5nm. Results are not compared below 5nm as Quantum effects are observed for channel thicknesses less than 5nm. ©2009 IEEE.

2009 2nd International Workshop on Electron Devices and Semiconductor Technology, IEDST '09

Modified surface potential based current modeling of thin silicon channel double gate SOI FinFETs

Deploying Systems Approach to Manage Employee Resistance to Change in Library and Information Centres : A Study of Library and Information Professionals ( LIPs ) of Academic and Research Sectors in India

Challenges for South Asian Resources and Information Services: Essays in {\ldots}

Development of Need Based Library and Information Science Curriculum: Emerging Global Trends, Opportunities and Challenges

Among the potential candidates for replacement of SiO2 or SiOxNy as gate dielectric [1], HfO2 seems to be one of the most promising materials [2-5], combining high dielectric permittivity with low leakage current due to a reasonably high barrier height that limits electron tunneling [6]. Other requirements [7-8] on gate dielectric materials like low density of interface states, gate compatibility, structural, physical and chemical stability at both gate electrode/dielectric and dielectric/silicon interfaces are currently making the object of intensive investigation for sub 0.1μm channel length devices using high-k dielectrics. The transition layer becomes important in such dielectrics in deciding the device performance. In this paper, we discuss the scaling limits of HfO 2/SiO2 stacked dielectrics taking into consideration the impact of transition layer between HfO2 and SiO2. In this paper, analysis of HfO2/SiO2 gate dielectric stack has been carried out for replacement of SiO2 using an appropriate direct-tunneling gate-current model. It has the potential to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies. © 2005 IEEE.

Proceedings of the IEEE International Conference on VLSI Design

Evaluation of device parameters of HfO2/SiO2/Si gate dielectric stack for MOSFETs

Parametric speech synthesizers utilize digital parameterized source-filter models for modeling the process of production of human speech. They are used in speech synthesis systems with an unlimited vocabulary. Presently, they are available as C language codes that run on PC platforms. They require a moderately high throughput of a mix of floating-point DSP functions and non-DSP (general-purpose) type computations. For embedded unlimited vocabulary speech synthesis systems, therefore, a need has been felt for the design of an Application Specific Integrated Processor for parametric speech synthesis. The present work describes the design of an Application Specific Instruction Set Processor (ASIP) for parametric speech synthesis that can serve the needs of embedded speech synthesis systems.