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Design of pseudo flip-around sample hold- circuit for 10-bit, 5-Msamples/sec pipeline ADC
M. Santosh, K.Ch. Behera,
Published in IEEE Computer Society
Pages: 100 - 103
This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 μm Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1mV, SNR of 60dB. The layout of the sample hold circuit occupies an area of 0.007mm2 and consumes 1.7 mW of power.