Recently, the industry has focused a great deal on the use of non-planar multi-gate device structures. Many drain current models are available for undoped thin silicon channel double-gate (DG) silicon-on-insulator (SOI) MOSFET, but these models do not take charge coupling effect into account leading to an error of more than 20 percent for silicon channel thicknesses below 30nm. Hence, we present here a modified drain current model based on the widely accepted and studied Ortiz-Conde suface potential model. The proposed model incorporates charge-coupling effect which comes into play in thin silicon channel multi-gate devices due to interaction of the multiple gates. The results of both the Ortiz-Conde's surface potential based model and the modified current model have been compared with simulated results obtained from Taurus-Davinci simulator. The modified model has an error percentage less than 4% even for channel widths as low as 5nm. Results are not compared below 5nm as Quantum effects are observed for channel thicknesses less than 5nm. ©2009 IEEE.