Department of Electrical Engineering

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IIT Jodhpur

This paper presents a theory and algorithms to select an appropriate driver node based on region of attraction (ROA) of single-input complex networks considering limited capacity of driver node. A single-input complex network is called controllable network if it can be driven from any initial state to desired state within finite time in n dimensional state space using a driver node. A driver node through which a network can be controlled is not unique. Non-uniqueness of driver node poses a challenge to select a right driver node when multiple possibilities exist. It is important to characterize these driver nodes and select the right driver node. In this paper, we consider a single-input unstable network with saturated actuator. © 2016 IEEE.

World University root node

2016 Indian Control Conference, ICC 2016 - Proceedings

Selection of driver nodes based on region of attraction for single-input complex networks

We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage ( VGS), gate length ( LG), substrate doping concentration ( Nsub), and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data. © 1963-2012 IEEE.

IEEE Transactions on Electron Devices

Modeling of Subsurface Leakage Current in Low VTH Short Channel MOSFET at Accumulation Bias

Recently, experimental Germanium CMOS devices and circuit are reported for advanced technology nodes for the first time. In this paper, we have modeled Germanium On Insulator (GeOI) device with industry standard compact model for independent double gate MOSFET (BSIM-IMG) with updated mobility model. It is shown that BSIM-IMG with updated mobility model accurately captures static characteristics for both n-channel and p-channel devices, and reproduces experimental CMOS inverter characteristics. This is the first time, when a compact model is validated on experimental CMOS circuit operation of GeOI. © 2016 IEEE.

2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016

Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model

This paper presents a revision of the existing universal image quality index (UIQ) metric in order to gauge the quality of images in a selective-processing iterative enhancement algorithm. The original UIQ is based on factors of loss of correlation, luminance and contrast similarity, and is, therefore, unsuitable in enhancement-related applications. While testing existing state-of-the-art metrics as image quality criterion in an iterative dynamic range compression algorithm, a lack of coherence was observed between the objective scores and that obtained from subjective evaluation study with twenty human subjects. We, therefore, propose to modify the existing UIQ with properties of a tone-mapped image. The proposed variant, named image quality metric for dynamic range compression, IQDRC, maintains the contributing effect of structural correlation and local contrast similarity, but observes an inverse relation with local luminance similarity. The proposed metric was observed to promisingly quantify the image quality and dynamic range compression of such images in close accordance with subjective scores for the target enhancement algorithm. Observations also suggest that IQDRC is indicative of image quality for various other dynamic range compression algorithms. © 2016 IEEE.

Image quality assessment for a selective-processing noise-aided iterative enhancement algorithm

Threshold voltage is an important device parameter for MOSFET modeling as circuit designer needs to know the threshold voltage to bias the transistor in the required region of operation. In this paper, we have proposed an approach to calculate the threshold voltage for operating point information in the BSIM-IMG model which is the latest industry standard compact model for FDSOI transistors. The BSIM-IMG is the surface potential based model, and therefore threshold voltage is not explicitly available. The proposed model takes care of back-bias and other real device effects (CLM, DIBL etc) accurately. The model is developed to fulfill the demand of semiconductor companies for their commercial SPICE simulators and PDKs. We have shown model comparison with various popular threshold voltage extraction techniques. The model shows very good agreement with the measured data over wide range of device geometries, drain and body biases. © 2016 IEEE.

Modeling of threshold voltage for operating point using industry standard BSIM-IMG model

Flexible organic field-effect transistors with high electrical stability upon bending are demonstrated on indium tin oxide coated polyethylene terephthalate substrates with TIPS-Pentacene semiconductor crystals formed by drop casting on a hybrid gate dielectric consisting hafnium dioxide grown by atomic layer deposition and spin coated poly(4-vinylphenol). Fabricated devices exhibited excellent p-channel characteristics with field-effect mobility up to 0.12cm2/Vs with high current on/off ratio &gt;104 and low threshold voltage of -0.2 V. Device performance was slightly affected by mechanical strain applied by bending for 5 min with radius varying from 12.5 mm to as low as 5.0 mm; and a high stability in performance was demonstrated upon applying constant tensile strain for more than 48 h at bending radius of 5.0 mm. It was found that strain induced changes in the device performance primarily occur due to increase in dielectric surface roughness; and the semiconductor-dielectric interface uniformity is influenced more with magnitude of strain rather than its duration. © 2016 Elsevier B.V. All rights reserved.

Organic Electronics

Flexible organic field-effect transistors with TIPS-Pentacene crystals exhibiting high electrical stability upon bending

Fabrication and optical sensing studies of single plane multi-zone nano-porous silicon (n-PS) prepared using laser-induced electrochemical etching technique is presented. Single plane multi-zone pertains to lateral formation of zones in silicon bearing step pore- and nano-crystallites size on the same plane. Different morphologies assembled in the form of a spiral shaped pattern on n-PS. Such novel pattern was a consequence of coupling between laser illumination and spiral shaped counter electrode used during silicon etching. The morphology analysis was done by recording profiles of characteristic LO phonon mode of silicon Raman spectra. The asymmetry and Raman peak shift helped in discerning the multi-zone morphology and it was complimented by Scanning Electron Microscopy (SEM) and photoluminescence (PL) studies. A wide range alcohol concentration (10-200 ppm) was tested using PL quenching technique. A direct correlation between morphology of n-PS and ethanol sensitivity was ascertained. Maximum sensing response of 40% was achieved at the centre and it decreased towards the periphery of the spiral pattern. The present simple and low cost fabrication technique allows fabrication of multiple morphologies on a single chip in one step and enables preparation of optimized n-PS for desirable applications. © 2016 Elsevier Ltd.

Materials and Design

Morphology dependent PL quenching of multi-zone nanoporous silicon: Size variant silicon nanocrystallites on a single chip

In this paper, a design of Substrate Integrated Waveguide (SIW) cavity backed slot antenna for polarization diversity application is presented. The proposed design uses a pair of slots placed at right angle with respect to each other at the top metallic plate of the cavity to generate two linear orthogonally polarized radiation pattern at same frequency to implement polarization diversity technique. The antenna interchanges between two separate feed line to excite either of the two orthogonal modes TE120 and TE210 respectively at same frequency and as a result, the proposed antenna exhibits a radiation pattern switching between Vertical (VP) and Horizontal Polarization (HP) at 9.98 GHz. The simulated result of the proposed design shows an isolation better than 20 dB between two input port and a gain of 4.2 dBi at broadside direction. © 2015 IEEE.

2015 IEEE Applied Electromagnetics Conference, AEMC 2015

Substrate Integrated Waveguide (SIW) cavity backed slot antenna for polarization diversity application

A novel design technique to implement dual band substrate integrated waveguide (SIW) cavity backed planar slot antenna is presented. The proposed antenna uses a combination of multiple SIW cavities of different size connected through coupling window in the common sidewall of the cavities. The cavities are loaded with long bow tie shaped slots to achieve higher bandwidth of the antenna. The placement of long bow tie slots helps to generate multiple hybrid modes which can be tuned by varying slot dimensions. First, two SIW cavities loaded with bow-tie slots are used to excite four closely placed hybrid modes in X band (8-12 GHz) to realise dual band response with a bandwidth of 600 MHz (7.2%) and 888 MHz (8.74%) and a gain of 5.3 and 4.4 dBi, respectively. The design is further extended using a set of four SIW cavities arranged as two pair of coupled SIW cavities along with bow-tie slots and placed in orthogonal orientation to implement dual band dual polarised slot antenna while maintaining its planar configuration. The proposed antenna exhibits a bandwidth of 390 MHz (3.9%) and 790 MHz (7.29%) with a gain of 6.1 and 5.4 dBi, respectively. © The Institution of Engineering and Technology 2016.

IET Microwaves, Antennas and Propagation

Design of dual band and dual-polarised dual band SIW cavity backed bow-tie slot antennas

In this paper, design of Substrate Integrated Waveguide (SIW) broadband unequal power divider is presented. A simple design technique to implement the unequal power division while maintaining a broad bandwidth is achieved only by changing the length of the step in the coupling region and H-plane matching step at the input while keeping all other dimensions same. A set of design curves are also presented to extend the proposed design technique to a large range of unequal power division. Two fabricated prototype of 1:4 and 1:8 power divider are presented which operate throughout the X band (8-12 GHz). © 2015 IEEE.