We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage ( VGS), gate length ( LG), substrate doping concentration ( Nsub), and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data. © 1963-2012 IEEE.

Harshit Agarwal

Department of Electrical Engineering

IIT Jodhpur

Y.-K. Lin

S. Khandelwal

A.S. Medury

H.-L. Chang

Y.S. Chauhan

C. Hu

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Modeling of Subsurface Leakage Current in Low $V_{\mathrm {TH}}$ Short Channel MOSFET at Accumulation Bias

IEEE Transactions on Electron Devices

Modeling of Subsurface Leakage Current in Low VTH Short Channel MOSFET at Accumulation Bias

Journal	Data powered by SciSpaceIEEE Transactions on Electron Devices
Publisher	Data powered by SciSpaceInstitute of Electrical and Electronics Engineers Inc.
ISSN	00189383