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Modeling of Subsurface Leakage Current in Low VTH Short Channel MOSFET at Accumulation Bias
Y.-K. Lin, S. Khandelwal, A.S. Medury, , H.-L. Chang, Y.S. Chauhan, C. Hu
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 63
Issue: 5
Pages: 1840 - 1845
We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage ( VGS), gate length ( LG), substrate doping concentration ( Nsub), and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data. © 1963-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Electron Devices
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.