IIT J Academic Staff

&ldquo;IIT Jodhpur is committed to impart quality education to facilitate the creation of qualified, competent and responsible human resources to meet the emerging technological challenges of the world. It is working towards creating an equitable learning platform that is positive, accessible and effective in the face of the modern societal and scientific advancements.

Flexibility in curriculum, in all its academic programs, encompassing elements of teaching, research, creativity, innovation and entrepreneurship is the most unique feature of IIT Jodhpur. The Department of Science and Technology (DST), under the National Mission on Cyber Physical Systems, has identified IIT Jodhpur as a Technology &amp; Innovation Hub in the area of Augmented Reality and Virtual Reality. The institute has also been nominated as the coordinator for the Jodhpur City and Knowledge Cluster by the Office of Principal Scientific Adviser, Government of India.

The sprawling 852-acre IIT Jodhpur campus is a majestic tribute to the deep-rooted diverse cultural heritage of the region. The campus is an architectural masterpiece, which is slated to become an international exemplar of sustainability with net-zero energy, and advanced water and waste management strategies.&rdquo;

IIT Jodhpur

The paper presents a simple circuit for piezo-resistive pressure sensors which compensates the temperature dependency of sensors. The output of piezo-resistive sensors generally, decreases with the increase in temperature when subjected to constant voltage excitation. To control the change with temperature, a varying excitation method is used. The proposed technique utilizes current steering DACs and a digital controller to compensate the variations. The technique is experimentally verified at hardware level where the digital control circuit is implemented on FPGA and tested with ASICs comprising of interface circuit. For the purpose of compensation, temperature is sensed using the same sensor. The temperature resolved is less than 1°C for a range of 10°C to 70°C with zero pressure correction technique. The test results for implementation show that the sensitivity and offset shift is compensated by a factor of 10 and 44 respectively. The complete fabricated chip, consisting of interface circuit and algorithm occupies 10 mm2 area. © Springer Nature Singapore Pte Ltd 2017.

World University root node

Communications in Computer and Information Science

Characterization and compensation circuitry for piezo-resistive pressure sensor to accommodate temperature induced variation

Proceedings of National Conference on Library Innovations for Excellence {\ldots}

From pathfinders to course guides: old wine in new bottle

Analog to Digital converters (ADC) are main design blocks for high efficiency medical applications. This paper represents a low power SAR ADC that uses a monotonic switching procedure in which switching occurs in one direction only thus switching energy reduces. As compared to conventional converter capacitance is reduced and Common mode voltage is also suppressed in the proposed method. So, dynamic latch comparator is being used to reduce the offset caused due to variation in the common mode voltage. A reliable low-distortion CMOS bootstrapped sampling switch is used. This work proposed asynchronous control logic technique to design low power, A/D converter that can be used for biomedical applications and does not employ any component trimming or adjustment. We achieved 1mW power dissipation for the proposed circuit. This architecture is simulated at 180nm technology using Cadence tool at 1.8Vsupply voltage. © 2016 IEEE.

2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Design &amp; simulation of successive approximation analog to digital converter using asynchronous control logic

A 12-bit low power successive approximation ADC has been designed and fabricated in 0.35 µm, poly–poly capacitor AMS technology. The SAR ADC is targeted for bridge type pressure sensor in wireless sensor node applications. An improved cascaded inverter based comparator is used for its lower power consumption at reduced supply voltage of 1.3 V. A modified SAR digital circuit has been incorporated to accommodate a higher input range of 1.8 V for the ADC. For a given noise floor, the higher input range of ADC ensures enhanced SNR performance relaxing the constraint on sensor interface circuit preceding to the ADC. Also a novel switching scheme is used in the feedback of comparator to reduce the charge injection induced offset without sacrificing the useful bandwidth of ADC. The inverter based comparator consumes 2 µW of power while operating at a speed of 1.6 MHz. The comparator does not make use of any offset cancellation techniques. By suitably choosing the capacitor array of inherent DAC, the calibration techniques have been avoided for the ADC. The ADC achieves an effective number of bits of 10.01 while consuming 6.69 µW at a conversion speed of 100 KHz. The FOM of the whole ADC is found to be 64.8 fJ/conversion-step. The active area occupied by the ADC is 0.170625 mm2 (375 µm × 455 µm). © 2015, Springer Science+Business Media New York.

Analog Integrated Circuits and Signal Processing

A low-power 12-bit SAR ADC for remote pressure measurement

This paper presents a 12-bit SA-ADC for portable low power wireless sensor systems. The proposed SA-ADC operates for rail-To-rail input range and achieves low power consumption. Split capacitor array based DAC and a novel charge-integration based dynamic comparator are used for low power consumption of the ADC. Measured DNL and INL are-0.59/0.67 LSB and-1.2/1.33 LSB respectively. At sampling rate of 100-kS/s with 1.8-V supply, the ADC consumes only 2-μW power and achieves a SNDR of 64.42-dB, SFDR of 71.2-dB resulting in an FoM of 14-fJ/Conversion-step. The ADC core occupies an area of 0.238-mm2 and is fabricated in AMS 0.35-μm CMOS technology. © 2016 IEEE.

2016 International Conference on VLSI Systems, Architectures, Technology and Applications, VLSI-SATA 2016

Ultra low power 12-Bit SAR ADC for wireless sensing applications

This paper describes a top-down approach to design a Sigma-Delta based modulator for analog to digital conversion. The primary focus is on designing an ADC for audio application, thus, the conversion is done on a 22.05 kHz bandwidth with a 16-bit resolution (CD quality). The behavioural code of the modulator is created first to check the signal ranges on internal nodes. Next, the circuit non-idealities, such as, finite Op-Amp gain, finite latency of Op-Amp and comparator offset are introduced to derive the tolerable limits and the specification of sub-blocks. Later, the individual blocks are carefully designed in 0.35 μm CMOS technology and are integrated. SPICE-based simulation is carried out on the entire circuit and the results are validated with MATLAB. © 2014 IEEE.

Proceedings of the 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014

Analysis and design of 2nd order sigma-delta modulator for audio applications

This paper presents a novel design methodology of a CMOS current starved ring Voltage Controlled Oscillator (VCO) for wide tuning range and high linearity. The f-V tuning characteristic of the ring VCO depends on the current-voltage (Ibias-Vcontrol) characteristic of the replica bias and region of operation of current sources/sinks transistors (CSTs). The proposed design methodology linearizes the Ibias-Vcontrolcharacteristic and ensures the CSTs to operate in saturation region during switching and consequently enhances the tuning range without additional circuitry. The design is implemented in UMC 0.18 μm CMOS technology at 1.8 V supply voltage. The overall circuit consumes 260 μW power at 404.5 MHz, has a wide tuning range of 66 MHz to 875 MHz having 94.5% tuning linearity. © Springer-Verlag Berlin Heidelberg 2013.

A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator

The proposed read-out circuit has a traditional two stage Operational amplifier (op-amp), a Gilbert cell and a Difference amplifier. The sensitivity of the sensor, known as primary with pressure variation can be increased with the help of an additional sensor, which act as a reference sensor. Here, we have used a current bias to increase the sensitivity. The current through both the sensors are controlled by a composite resistor and an op-amp having 70db PSRR. The advantage of using composite resistor is its immunity to process variation as well as stabilization of current sourced into the sensors. The simulation of the sensor along with the read out bias circuit is performed in cadence environment with AMS (Austria Microsystems) 0.35 μm technology design kit. The simulation for in-house fabricated MEMS pressure sensor is done by macro-modeling. The simulated output of the read-out circuit along with the macro model of sensor is showing almost rail-to rail output swing (around 3 V for a 3.3 V supply). The total power dissipation (including the sensor) is less than 10 mW for a 3 mA bias current. The total area occupied by the readout circuit is less than 0.04 mm 2. MEMS pressure sensor was fabricated by SNG group of CEERI, fabricated sensor occupies 0.14 mm 2 of area. © 2012 IEEE.

2012 International Conference on Devices, Circuits and Systems, ICDCS 2012

Design of an on chip read-out circuit for piezo-resistive MEMS pressure sensor

The chapter discusses library support services in a distance education system and their value and importance in the overall development of a learner in general and a distance learner in particular. The chapter also traces how emerging digital technologies allow libraries to offer efficient support services to distance learners. This case of Distance Library Services at a university in India describes the evolution, experiences and challenges of offering distance library services through the university. The chapter focuses on information literacy and use of social networking tools. Development of information literacy is critical for distance learners and social networking tools based on Web 2.0 technologies may provide library services and impart information literacy to distance learners. The chapter concludes with some suggestions pertaining to opportunities and future propositions.

Cases on Building Quality Distance Delivery Programs: Strategies and {\ldots}

Library Support to Distance Learners: Case of a University's Distance Library Services in India

Journal of Emerging Trends in Computing and Information Sciences

A Systems Approach for Dealing with Resistance to Change: With Reference to Library and Information Professionals Working in Academic and Research Sector Libraries in India