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Towards row sensitive dram refresh through retention awareness
T. Goel, D. Maura, K. Goswami, S. Das,
Published in IEEE Computer Society
Volume: 2021-April
Pages: 450 - 456
Dynamic Random Access Memory (DRAM) is the de-facto choice for main memories in modern day computing systems. It is based on capacitor technology, which is volatile in nature. Hence, these memories require periodic refreshing, usually at 64 ms, in order to ensure data persistence. Refreshing results in blocking of the memory device for performing normal read or write operations. However, it has been found that not all cells of the device requires uniform refreshing at 64 ms. Due to shrinking of technologies, deviations are observed in nominal parameters which causes variations in retention and restoration time. In this paper, we propose a retention aware DRAM refreshing model, which is operated in auto-refresh (AR) mode of a DRAM device. We call the proposed model Lightweight Retention Time Aware Refreshing, or simply LRAR, which can be operated either in a deterministic or an approximate mode while consuming a constant amount of hardware space. The former ensures consumption of least possible area in comparison to previously proposed works. While the latter is aimed to incorporate periodic refreshing for a newly emerged DRAM phenomenon called Variable Retention Time, or, VRT, which uses the basics of approximation. After extensive evaluation, we find that our proposed model reduces execution time of programs up to 11% (9.4% on average). The memory system's energy consumption is also reduced by an average of 11.5%, and refresh energy by an average of 73.6%. We achieve the aforementioned gains at a modest area overhead of 7$, 240 \mu \mathrm{m}^{2}\, (0.0018$% of a 400mm$^{2\, }$die) and storage overhead. © 2021 IEEE.
About the journal
JournalData powered by TypesetProceedings - International Symposium on Quality Electronic Design, ISQED
PublisherData powered by TypesetIEEE Computer Society