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Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG
P. Kushwaha, K. Bala Krishna, , S. Khandelwal, J.-P. Duarte, C. Hu, Y.S. Chauhan
Published in Elsevier Ltd
Volume: 56
Pages: 171 - 176
The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors. © 2016 Elsevier Ltd
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JournalData powered by TypesetMicroelectronics Journal
PublisherData powered by TypesetElsevier Ltd