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Silicon nanowire: Technology platform, devices, applications and challenges
G.Q. Lo, N. Singh, S.C. Rustagi, H.S. Nguyen, L.K. Bera, W.W. Fang, , C.H. Tung, N. Balasubramanian, D.L. Kwong
Published in
Volume: 6
Issue: 1
Pages: 73 - 86
This paper gives a brief overview of the semiconductor nanowires, in particular the Si- and Ge-nanowires, and summarizes the status of CMOS-compatible nanowire devices. Results were based on the research conducted recently in the Institute with the nanowire technology platform. To facilitate the realization of controllable, scalable and increasing functionality, top-down approach was adopted for the platform establishment on our 8'' CMOS fabrication line. Gate-All-Around (GAA) nanowire FET is chosen as test vehicle, which is projected as the final architecture carrying the CMOS towards the end-of-the-roadmap for Si-devices. Fabrication technology is presented with various gate stacks. Excellent transistor characteristics of GAA Si-nanowire FETs are illustrated with near-ideal subthreshold, low DIBL, high ION/IOFF, accompanied with the demonstration of high gain CMOS Inverter. Impact of low temperature on device behavior is discussed. Ge-wire devices are also presented along with the well behaved vertically stacked device structures. Lastly, the challenges are also discussed. © The Electrochemical Society.
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JournalECS Transactions