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Proposal for capacitance matching in negative capacitance field-effect transistors
, P. Kushwaha, Y.-K. Lin, M.-Y. Kao, Y.-H. Liao, A. Dasgupta, S. Salahuddin, C. Hu
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 40
Issue: 3
Pages: 463 - 466
Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance {C}-{\textsf {fe}} and the underlying MOS transistor {C}-{\textsf {MOS}}. Since both {C}-{\textsf {MOS}} and {C}-{\textsf {fe}} have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of {C}-{\textsf {fe}} The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-Threshold swing as well as lower power supply {V}-{\textsf {dd}} compared with a prototype single-layer negative-capacitance field-effect transistor. © 1980-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Electron Device Letters
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.