We present a charge-based compact model for induced gate thermal noise for a fully depleted silicon-on-insulator transistor. The model uses front- and back-gate charges as well as the respective mobilities for the development of analytical expression. The model is implemented in Verilog-A and validated with experimentally calibrated TCAD simulations. The model predicts the high-frequency behavior with good accuracy while capturing the back-bias dependence. © 2001-2012 IEEE.

Harshit Agarwal

Department of Electrical Engineering

IIT Jodhpur

C.K. Dabhi

A. Dasgupta

P. Kushwaha

C. Hu

Y.S. Chauhan

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Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET

IEEE Microwave and Wireless Components Letters

Journal	Data powered by TypesetIEEE Microwave and Wireless Components Letters
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	15311309