There is a growing demand for low power error control decoders that are widely used in communication systems. One of the key component in a turbo error control decoder used to decode turbo codes-the Shannon limit approaching code- is a Max-Log-MAP decoder. To scale down the power and area used by the conventional Add-Compare-Select (ACS) module of the Max-Log-MAP decoder, a modified version of the ACS, known as Compare-Add-Select (CSA) has been used in this paper. The scale down is accomplished by reducing the number of operations used in calculating the path metrics of the Max-Log-MAP decoder. The observations assert that for the proposed architecture, there is a 50% reduction in both area and power without compromising the performance when compared to the conventional architecture. © 2018 IEEE.