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Jitter failure investigation of high speed parallel links in System on Chip environment, modeling and mitigation approach
R.K. Nagpal, P. Damle, , R. Malik, J. Mukherjee
Published in UBM Electronics
This paper proposes methodology for generic system modelling of high speed parallel interfaces. The paper also covers case study of Clock jitter failure analysis in Double data rate Physical layer (DDR2/3) in SOC environment. This Methodology involves breaking down the system in multiple components and generating models for each component to observe individual performance. System level response can be seen by combining them together. This is validated for root- cause analysis and corrections on a reference SoC along with its application environment. Using this methodology, Silicon results before and after corrections on SoC indicate desired improvements. The worthiness of this approach exhibits a pre-compliance design step to avoid silicon respins and failures.
About the journal
JournalDesignCon 2015
PublisherUBM Electronics