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I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)
M. Souilem, , W. Dghais, H. Belgacem
Published in IEEE Computer Society
Volume: 2019-October
Pages: 226 - 227
This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output buffers. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum prediction error for the peak to peak values of eye jitter and eye height are 7.06 and 2.59, respectively. © 2019 IEEE.
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JournalData powered by TypesetIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
PublisherData powered by TypesetIEEE Computer Society