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Hardware Design of a Turbo Product Code Decoder
G.C. Nair, B. Yamuna, K. Balasubramanian,
Published in Springer Science and Business Media Deutschland GmbH
Volume: 728 LNEE
Pages: 249 - 255
In a communication channel, message transfer happens through a noisy medium which can introduce errors in the transmitted message. It is required to maintain an acceptable bit error rate for a reliable transmission. This can be handled by an efficient error control coding scheme. This paper discusses the hardware design of an error control decoder, namely turbo product code decoder. The iterative Chase-Pyndiah decoding algorithm has been used in the turbo decoder design. The decoder has been designed using both MATLAB and Verilog, and its performance has been analysed. To study the robustness of the decoder in dealing with different data types, performance analysis is done with both the received data and the encrypted version of the same. Advanced Encryption Standard (AES) has been used for the encryption process, and it is shown that there is only a negligible difference in the performance for both the data sets. © 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About the journal
JournalData powered by TypesetLecture Notes in Electrical Engineering
PublisherData powered by TypesetSpringer Science and Business Media Deutschland GmbH