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FPGA based implementation of a floating point multiplier and its hardware trojan models
S. Nikhila, B. Yamuna, K. Balasubramanian,
Published in Institute of Electrical and Electronics Engineers Inc.
Floating point multiplication plays a crucial role in computationally intensive applications like digital signal processing. This paper deals with the design of a single precision floating point multiplier and its FPGA realization with LCD interface for output display. To bring out the need for secure hardware design, hardware Trojan models are proposed for the mantissa multiplication unit of the floating point multiplier. Implementation results show that the Trojans produce an average difference of 15%-20% in the product values, an increase of on-chip power by 1.61% and an increase of 0.4% in the number of LUTs. The negligible change in the area and power dissipated establishes the stealthy nature of the proposed Trojans. © 2019 IEEE.