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Fast analysis of time interval error in current-mode drivers
, R. Achar, R. Malik
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 26
Issue: 2
Pages: 367 - 377
—An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach. © 2017 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Very Large Scale Integration (VLSI) Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.