This paper presents an analysis of jitter in a CMOS inverter due to power supply, ground bounce and substrate noise. The analysis is based on the recently introduced method EMPSIJ  which is extended in this paper for substrate noise induced jitter. To estimate jitter due to various noise sources (such as supply noise, ground bounce, substrate noise), noise transfer functions are derived. The results of EMPSIJ and the EDA simulations are compared for an inverter designed in a 28nm CMOS Technology of TSMC. For multiple test cases, the results match reasonably well with mean percentage error (MPE) not exceeding 10%. © 2018 IEEE.