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Efficient Jitter Analysis for a Chain of CMOS Inverters
, P. Arora, H. Shrimali, R. Achar
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 62
Issue: 1
Pages: 229 - 239
This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy. © 2018 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Electromagnetic Compatibility
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.