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Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters
P. Arora, , H. Shrimali
Published in Institute of Electrical and Electronics Engineers Inc.
This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter. IEEE
About the journal
JournalData powered by TypesetIEEE Transactions on Electron Devices
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.