Negative capacitance field effect transistor (NCFET) is designed in 5-nm FinFET node, which simultaneously meets the low-power and high-performance targets of ION and IOFF at Vdd = 0.5 V and Vdd = 0.23 V, respectively, while the international roadmap for devices and systems (ITRS 2.0) projected Vdd is 0.65 V for both. The impact of power supply and parasitic capacitance on the performance of NCFET is studied. It is demonstrated that NCFET can be designed for fluid subthreshold swing (SS) behavior such that SS is degraded around Vgs = 0, Vds = Vdd, and is improved in the subthreshold region. This helps in combating OFF-current variation due to the threshold voltage fluctuations. A compact model to determine such design conditions is presented. Parasitic capacitance and the ferroelectric material parameters should be cooptimized for the target Vdd. © 1963-2012 IEEE.

Harshit Agarwal

Department of Electrical Engineering

IIT Jodhpur

P. Kushwaha

J.P. Duarte

Y.-K. Lin

A.B. Sachid

H.-L. Chang

S. Salahuddin

C. Hu

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Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

IEEE Transactions on Electron Devices

Designing 0.5 v 5-nm HP and 0.23 v 5-nm LP NC-FinFETs with Improved IOFF Sensitivity in Presence of Parasitic Capacitance

Journal	Data powered by TypesetIEEE Transactions on Electron Devices
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	00189383