In the field of digital communication, there has always been a requirement for an efficient, low complex, and high-speed error control encoder and decoder. Many such encoders and decoders for different error control codes have been proposed in the literature by researchers. However, developing such CODECs whose performance can be suitable for the requirements of modern communication systems is still an open research problem. In this paper, one such decoder, namely fast Chase decoder proposed in the literature, has been studied. The hardware design of the decoder has been done and verified with results from MATLAB simulations. An attempt has been made to improve the speed by replacing the ripple carry adder in the design with a fast adder. The hardware architecture is implemented in Xilinx XC7A35T platform, and an increase in computation speed of 5% has been achieved. © 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.