This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE). © 2019 IEEE

Jai Narayan Tripathi

Department of Electrical Engineering

IIT Jodhpur

V.K. Sharma

B. Dinesh Kumar

M.S. Illikkal

N. Gupta

H. Shrimali

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Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

Proceedings - IEEE International Symposium on Circuits and Systems

Analysis of timing error due to supply and substrate noise in an inverter based high-speed comparator

Journal	Data powered by TypesetProceedings - IEEE International Symposium on Circuits and Systems
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	02714310