This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc. © 2013 IEEE.

Jai Narayan Tripathi

Department of Electrical Engineering

IIT Jodhpur

M.S. Illikkal

H. Shrimali

R. Achar

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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

IEEE Access

A thomas algorithm-based generic approach for modeling of power supply induced jitter in CMOS buffers

Journal	Data powered by TypesetIEEE Access
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN	21693536